Known integrated memory arrays generally have a fixed depth and fixed width as associated with a given data storage application. Accordingly, different data storage applications may require separate respective memory arrays for meeting the different depth/width requirements. However, it would be advantageous if a single memory resource were capable of meeting the different depth/width application needs.
A variety of known memory devices are available for providing different memory access techniques. The most common memory access technique includes simple addressable read/write memory functionality. Other access techniques include LIFO (Last In First Out), FIFO (First In First Out) and rollover data stack operations. Existing data storage devices are generally tailored to specific, fixed access techniques. However, it would be advantageous if a memory device were programmable to selectively provide combinations of access techniques.
Programmable integrated circuits are known in the art and include programmable gate arrays (PGA) which provide an array of distinct, uncommitted logic cells. A programmable interconnect network is usually provided for interconnecting the cells and/or to provide data input to and output from the array. Customization or programming of the otherwise generally designed logic cells and interconnect network is performed for implementing a particular application. One such device is a field-programmable gate array (FPGA), wherein the configuration of the FPGA can be performed by a user "in the field." The configuration of the FPGA is effected by using electrically programmable fusible links, anti-fuses, memory controlled transistors or floating gate transistors. To program the FPGA, configuration data is transferred from an external memory device to electrically programmable resources of the FPGA. As densities of these field programmable gate arrays increase, the demand for on-board memory/storage functionality likewise increases. Accordingly, it would be desirable to provide an integrated circuit including an FPGA together with a programmable memory array, which memory array could be capable of implementing various configurations, and/or provide one of a variety of memory access techniques.